Verilog-A release version.
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.

26 lines
756 B

//VerilogA for passive,spliter3,veriloga
`include "constants.vams"
`include "disciplines.vams"
module spliter3(Ipow,Iphase,Ilam,Opow1,Ophase1,Olam1,Opow2,Ophase2,Olam2,Opow3,Ophase3,Olam3);
parameter real r1 = 0.3333 from [0:1];
parameter real r2 = 0.3333 from [0:1];
parameter real r3 = 0.3333 from [0:1];
input Ipow,Iphase,Ilam;
output Opow1,Ophase1,Olam1,Opow2,Ophase2,Olam2,Opow3,Ophase3,Olam3;
electrical Ipow,Iphase,Ilam,Opow1,Ophase1,Olam1,Opow2,Ophase2,Olam2,Opow3,Ophase3,Olam3;
analog begin
V(Opow1) <+ V(Ipow)*r1;
V(Opow2) <+ V(Ipow)*r2;
V(Opow3) <+ V(Ipow)*r3;
V(Ophase1) <+ V(Iphase);
V(Ophase2) <+ V(Iphase);
V(Ophase3) <+ V(Iphase);
V(Olam1) <+ V(Ilam);
V(Olam2) <+ V(Ilam);
V(Olam3) <+ V(Ilam);
end
endmodule