//VerilogA for modulator,idealea,veriloga

`include "constants.vams"
`include "disciplines.vams"

module idealea(Ipow,Iphase,Ilam,Opow,Ophase,Olam,Vdata);
    parameter real modu = 0.9 from [0:1);
    parameter real chir = 0 from (-inf:inf);

    input Ipow,Iphase,Ilam,Vdata;
    output Opow,Ophase,Olam;
    electrical Ipow,Iphase,Ilam,Opow,Ophase,Olam,Vdata;

    real dt;
    analog begin
        dt = (1-modu)+modu*V(Vdata);
        V(Opow) <+ V(Ipow)*dt;
        V(Ophase) <+ V(Iphase)+chir/2.0*ln(dt)*360.0/(2*`M_PI);
        V(Olam) <+ V(Ilam);
    end


endmodule