//VerilogA for passive,phasedelay,veriloga
`include "constants.vams"
`include "disciplines.vams"

module phasedelay(V1,V2,Ipow,Iphase,Ilam,Opow,Ophase,Olam);
	parameter real a = 1;
	parameter real phi = 0 from (-360:360);

	input Ipow,Iphase,Ilam;
	output Opow,Ophase,Olam;
	inout V1,V2;
	electrical V1,V2,Ipow,Iphase,Ilam,Opow,Ophase,Olam;

	real iph,oph;

	analog begin
		iph=I(Iphase)/360.0*2*`M_PI;
		oph=(iph+a*(V(V1)-V(V2))+phi/360.0*2*`M_PI)*360.0/(2*`M_PI);
		V(Opow) <+ V(Ipow);
		V(Ophase) <+ oph;
		V(Olam) <+ V(Ilam);
	end

endmodule