//VerilogA for tools,randbit,veriloga

`include "constants.vams"
`include "disciplines.vams"

module randbit(Vout);
    parameter integer seed = 216529;
    parameter real trise = 0 from [0:inf);
    parameter real tfall = 0 from [0:inf);
    parameter real tdelay = 0 from [0:inf);
    parameter real tpulse = 1 from (0:inf);
    parameter real vlow = 0 from (-inf:inf);
    parameter real vhigh = 1 from (-inf:inf);
    output Vout;
    electrical Vout;

    real ctime,v;
    real bit=0;
    integer iseed=seed;
    analog begin
        @(initial_step) begin
            v=vlow;
            ctime=$abstime+tpulse;
        end

        @(timer(ctime)) begin
            bit=$random(iseed) & 1;
            v=(vhigh-vlow)*bit+vlow;
            ctime=$abstime+tpulse;
        end

        V(Vout) <+ transition(v,tdelay,trise,tfall);
    end
endmodule