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49 lines
1.2 KiB
49 lines
1.2 KiB
7 months ago
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//VerilogA for tools,randbit_pam4,veriloga
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`include "constants.vams"
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`include "disciplines.vams"
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module randbit_pam4(Vout);
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parameter integer seed1 = 418674;
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parameter integer seed2 = 416352;
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parameter integer seed3 = 241412;
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parameter real trise = 0 from [0:inf);
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parameter real tfall = 0 from [0:inf);
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parameter real tdelay = 0 from [0:inf);
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parameter real tpulse = 1 from (0:inf);
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parameter real vlow = 0 from (-inf:inf);
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parameter real vpulse = 1 from (-inf:inf);
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output Vout;
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electrical Vout;
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real ctime,v,v1,v2,v3;
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real bit1=0;
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real bit2=0;
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real bit3=0;
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integer iseed1=seed1;
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integer iseed2=seed2;
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integer iseed3=seed3;
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analog begin
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@(initial_step) begin
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v=vlow;
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v1=0;
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v2=0;
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v3=0;
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ctime=$abstime+tpulse;
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end
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@(timer(ctime)) begin
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bit1=$random(iseed1) & 1;
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bit2=$random(iseed2) & 1;
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bit3=$random(iseed3) & 1;
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v1=(vpulse)*bit1;
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v2=(vpulse)*bit2;
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v3=(vpulse)*bit3;
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v=v1+v2+v3+vlow;
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ctime=$abstime+tpulse;
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end
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V(Vout) <+ transition(v,tdelay,trise,tfall);
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end
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endmodule
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