Verilog-A release version.
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7 months ago
//VerilogA for tools,randbit_pam4,veriloga
`include "constants.vams"
`include "disciplines.vams"
module randbit_pam4(Vout);
parameter integer seed1 = 418674;
parameter integer seed2 = 416352;
parameter integer seed3 = 241412;
parameter real trise = 0 from [0:inf);
parameter real tfall = 0 from [0:inf);
parameter real tdelay = 0 from [0:inf);
parameter real tpulse = 1 from (0:inf);
parameter real vlow = 0 from (-inf:inf);
parameter real vpulse = 1 from (-inf:inf);
output Vout;
electrical Vout;
real ctime,v,v1,v2,v3;
real bit1=0;
real bit2=0;
real bit3=0;
integer iseed1=seed1;
integer iseed2=seed2;
integer iseed3=seed3;
analog begin
@(initial_step) begin
v=vlow;
v1=0;
v2=0;
v3=0;
ctime=$abstime+tpulse;
end
@(timer(ctime)) begin
bit1=$random(iseed1) & 1;
bit2=$random(iseed2) & 1;
bit3=$random(iseed3) & 1;
v1=(vpulse)*bit1;
v2=(vpulse)*bit2;
v3=(vpulse)*bit3;
v=v1+v2+v3+vlow;
ctime=$abstime+tpulse;
end
V(Vout) <+ transition(v,tdelay,trise,tfall);
end
endmodule