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35 lines
852 B
35 lines
852 B
7 months ago
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//VerilogA for tools,randbit,veriloga
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`include "constants.vams"
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`include "disciplines.vams"
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module randbit(Vout);
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parameter integer seed = 216529;
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parameter real trise = 0 from [0:inf);
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parameter real tfall = 0 from [0:inf);
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parameter real tdelay = 0 from [0:inf);
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parameter real tpulse = 1 from (0:inf);
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parameter real vlow = 0 from (-inf:inf);
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parameter real vhigh = 1 from (-inf:inf);
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output Vout;
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electrical Vout;
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real ctime,v;
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real bit=0;
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integer iseed=seed;
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analog begin
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@(initial_step) begin
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v=vlow;
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ctime=$abstime+tpulse;
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end
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@(timer(ctime)) begin
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bit=$random(iseed) & 1;
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v=(vhigh-vlow)*bit+vlow;
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ctime=$abstime+tpulse;
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end
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V(Vout) <+ transition(v,tdelay,trise,tfall);
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end
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endmodule
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