Verilog-A release version.
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7 months ago
//VerilogA for passive,spliter2,veriloga
`include "constants.vams"
`include "disciplines.vams"
module spliter2(Ipow,Iphase,Ilam,Opow1,Ophase1,Olam1,Opow2,Ophase2,Olam2);
parameter real r1 = 0.5 from [0:1];
parameter real r2 = 0.5 from [0:1];
input Ipow,Iphase,Ilam;
output Opow1,Ophase1,Olam1,Opow2,Ophase2,Olam2;
electrical Ipow,Iphase,Ilam,Opow1,Ophase1,Olam1,Opow2,Ophase2,Olam2;
analog begin
V(Opow1) <+ V(Ipow)*r1;
V(Opow2) <+ V(Ipow)*r2;
V(Ophase1) <+ V(Iphase);
V(Ophase2) <+ V(Iphase);
V(Olam1) <+ V(Ilam);
V(Olam2) <+ V(Ilam);
end
endmodule