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25 lines
546 B
25 lines
546 B
7 months ago
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//VerilogA for passive,phasedelay,veriloga
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`include "constants.vams"
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`include "disciplines.vams"
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module phasedelay(V1,V2,Ipow,Iphase,Ilam,Opow,Ophase,Olam);
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parameter real a = 1;
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parameter real phi = 0 from (-360:360);
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input Ipow,Iphase,Ilam;
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output Opow,Ophase,Olam;
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inout V1,V2;
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electrical V1,V2,Ipow,Iphase,Ilam,Opow,Ophase,Olam;
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real iph,oph;
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analog begin
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iph=I(Iphase)/360.0*2*`M_PI;
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oph=(iph+a*(V(V1)-V(V2))+phi/360.0*2*`M_PI)*360.0/(2*`M_PI);
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V(Opow) <+ V(Ipow);
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V(Ophase) <+ oph;
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V(Olam) <+ V(Ilam);
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end
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endmodule
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