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24 lines
573 B
24 lines
573 B
7 months ago
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//VerilogA for modulator,idealea,veriloga
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`include "constants.vams"
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`include "disciplines.vams"
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module idealea(Ipow,Iphase,Ilam,Opow,Ophase,Olam,Vdata);
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parameter real modu = 0.9 from [0:1);
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parameter real chir = 0 from (-inf:inf);
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input Ipow,Iphase,Ilam,Vdata;
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output Opow,Ophase,Olam;
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electrical Ipow,Iphase,Ilam,Opow,Ophase,Olam,Vdata;
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real dt;
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analog begin
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dt = (1-modu)+modu*V(Vdata);
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V(Opow) <+ V(Ipow)*dt;
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V(Ophase) <+ V(Iphase)+chir/2.0*ln(dt)*360.0/(2*`M_PI);
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V(Olam) <+ V(Ilam);
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end
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endmodule
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